Implementation, Operation Analysis, and Performance Evaluation for a Wishbone-Based System-on-Chip
Corressponding author's email:
khoapv@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.76.2023.1122Keywords:
System on chip, Wishbone, Arbiter, Operation frequency, Power consumptionAbstract
As integrated circuit technology advances, many processing cores can be built into a single silicon chip. This method optimizes design parameters like cost, size, and power consumption. Integrated circuit solutions support multiple connection types and shared interfaces for the cores to standardize data communication. Several popular buses, such as CoreConnect, AMBA, SiliconBackplane, and Wishbone, have been developed to accommodate many processor cores. The main challenge in designing the bus architecture is determining how to connect the processing cores in a simple, flexible, and scalable manner. Among the proposed methods, Wishbone architecture is a highly efficient solution for linking cores. This study implemented, analyzed, and evaluated the performance of a Wishbone-based System-on-Chip using simulation waveforms and FPGA hardware implementation to demonstrate the effectiveness of the Wishbone architecture in SoC design. According to simulation and realization results, Wishbone has a simple structure, requires fewer hardware resources, and is scalable for multi-core designs.
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