Carrier PWM algorithm for five-level H-brigde npc inverter with switching reduction

Authors

  • Thanh Hai Quach Ho Chi Minh City University of Technology and Education, Vietnam
  • Thu Ha Tran Ho Chi Minh City University of Technology and Education, Vietnam
  • Tuan Le Danh Kien Giang Technical - Economic College, Vietnam
  • Duc Tri Do Ho Chi Minh City University of Technology and Education, Vietnam
  • Huynh Ly Le Hue Industrial College, Vietnam

Corressponding author's email:

haiqt@hcmute.edu.vn

Keywords:

carrier pulse width modulation, novel offset, reduce number of switching times, inverter

Abstract

This paper presents the carrier pulse width modulation with a novel offset based to re- duce the number of switching times in a five-level H-bridge neutral point clamped inverter. The proposed technique uses the offset which is 3rd voltage component to shift the control voltage signal to the maximum or minimum amplitude of the carrier in order to reduce the intersection of the control signals and the carrier wave and thus to reduce the number of switching times. With the pulse width modulation method and flexible offset voltages in this study, the number of switching times/phase in a cycle can be reduced to 33%. Simulation and experimental results are provided in order to validate the proposed method.

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References

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Published

28-12-2015

How to Cite

[1]
T. H. Quach, . T. H. Tran, . T. L. Danh, Đức T. Do, and H. L. Le, “Carrier PWM algorithm for five-level H-brigde npc inverter with switching reduction”, JTE, vol. 10, no. 4, pp. 36–41, Dec. 2015.

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Research Article

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