FPGA-Based Design and Implementation of CRC-16 Encoder and Decoder
Corressponding author's email:
tandd@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.71B.2022.1140Keywords:
CRC, FPGA, Verilog, Encoder, DecoderAbstract
Error control coding is an important functional block to ensure the reliability of any communication system. Specifically, Cyclic Redundancy Check (CRC) codes are widely used in many fields such as civil communication and industrial communication. CRC codes efficiently provide the first layer of protection against data corruption during data transmission sent from a transmitter to a receiver over channels. With the advantage of being simple but effective in detecting and possibly correcting errors in data transmission and storage of digital data. In this paper, we present a detailed design and implementation of a CRC-16 encoder and decoder based on Field Programmable Gate Array (FPGA) using Verilog hardware description language. Then, we evaluate the design using both Xilinx ISE software and AX309 FPGA kit where error detection capability and resource usage are tested in detail. Extensive simulations and FPGA board based experimental results have been conducted to confirm the effectiveness of our proposed design.
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