FPGA-Based Design and Implementation of 16-Point FFT Calculator

Authors

  • Van Thanh Loc Nguyen Ho Chi Minh City University of Technology and Education, Vietnam
  • Truong Huu Thuong Hoang Ho Chi Minh City University of Technology and Education, Vietnam
  • Thi Hoai Nhi Mai Ho Chi Minh City University of Technology and Education, Vietnam
  • Duy Tan Do Ho Chi Minh City University of Technology and Education, Vietnam

Corressponding author's email:

tandd@hcmute.edu.vn

DOI:

https://doi.org/10.54644/jte.71B.2022.1139

Keywords:

16-point FFT, FPGA, R2SDF, Pipeline, Testbench

Abstract

This paper presents a design and construction of a 16-point FFT calculator based on FPGA technology. Specifically, the data is complex numbers in which the real and imaginary parts are represented as fixed-point real numbers. Moreover, a fixed-point real number is defined by 16 bits with the high-significant bit being the 2's complement bit, the next 9 bits being the integer part, and the last 6 bits being the fractional part. By means of simulations and FPGA board-based experimental results, we show the advantage of the proposed design compared to the existing ones. The operating frequency of the system is 149,867 MHz giving 4,683,343 FFT calculations of 16-points per second with low error (only about 0.3). This design of FFT calculator could be extensible to perform multi-point transformations since it is designed in a pipeline architecture with modules that are easily resizable and can be embedded in systems that require the 16-point FFT calculator.

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Author Biographies

Van Thanh Loc Nguyen, Ho Chi Minh City University of Technology and Education, Vietnam

Nguyen Van Thanh Loc received his B.S degree from Ho Chi Minh City University of Technology and Education (HCMUTE), Vietnam, in 2020. His main research interests include communication networks and applications of error-control coding for wireless communications.

Truong Huu Thuong Hoang, Ho Chi Minh City University of Technology and Education, Vietnam

Hoang Truong Huu Thuong received his B.S degree from Ho Chi Minh City University of Technology and Education (HCMUTE), Vietnam, in 2021. His main research interests include communication networks and FPGA-based design for DSP applications.

Thi Hoai Nhi Mai , Ho Chi Minh City University of Technology and Education, Vietnam

Mai Thi Hoai Nhi received his B.S degree from Ho Chi Minh City University of Technology and Education (HCMUTE), Vietnam, in 2021. Her main research interests include wireless communication networks and FPGA-based designs for DSP applications.

Duy Tan Do, Ho Chi Minh City University of Technology and Education, Vietnam

Do Duy Tan received his B.S. degree from Ho Chi Minh City University of Technology (HCMUT), Vietnam, and M.S. degree from Kumoh National Institute of Technology, Korea, in 2010 and 2013, respectively. He received his Ph.D. degree from Autonomous University of Barcelona, Spain, in 2019. He is currently with the Department of Computer and Communication Engineering, Ho Chi Minh City University of Technology and Education (HCMUTE) in Vietnam as an Assistant Professor. His main research interests include real-time optimisation for resource allocation in wireless networks and coding applications for wireless communications.

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Published

30-08-2022

How to Cite

[1]
V. T. L. Nguyen, T. H. T. Hoang, T. H. N. Mai, and D. T. Do, “FPGA-Based Design and Implementation of 16-Point FFT Calculator ”, JTE, vol. 17, no. Special Issue 02, pp. 10–18, Aug. 2022.

Issue

Vol. 17 No. Special Issue 02 (2022)

Section

Research Article

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