Design and verification of serial interface engine module in usb standard
Corressponding author's email:
tandd@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.65.2021.145Keywords:
Serial Interface Engine, USB 2.0, FPGA, Xilinx ISE, verificationAbstract
This paper presents a design and verification of a Serial Interface Engine (SIE) module in the USB 2.0 standard based on FPGA technology. The SIE unit receives data sent from the Central Processing Unit (Central Processing Unit or CPU) and passes it to the Universal Transceiver Macrocell Interface (UTMI). At the sender, the data is converted from parallel to serial, then passed through the error control encoder and the channel encoder before being transmitted over the channel. At the receiver, on the contrary, after going through the channel decoder and the error control decoder, the serial data is converted back to parallel. By means of various simulations, we show that the operation of the designed SIE module fully meets the technical requirements.
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References
Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips, “Universal Serial Bus Specification”, Revision 2.0, April 27, 2000.
L. Nardozza, “USB-IF Offers Guidance to Industry for Design Compliance of USB Devices,” USB Implementers Forum (USB-IF), Barcelona, Spain, Feb. 21, 2016, pp. 1-3, http://www.usb.org/.
A. Bouhraoua and M. Al-Shammari, “A fundamentally secure payment device interfaced to regular PCs,” in Proc. IEEE Region Conf., Kansas, MO, USA, Apr. 2008, pp. 1-5. DOI: https://doi.org/10.1109/TPSD.2008.4562736
P. M. Szecowka and K. J. Pyrzynski, “USB receiver/transmitter for FPGA implementation,” 2012 International Conference on Signals and Electronic Systems (ICSES), Poland, Sep. 2012, pp. 1-6. DOI: https://doi.org/10.1109/ICSES.2012.6382226
S. Kaul, P. Maheta, R. J. Rajesh and R. R. Das, "Novel multi-interface USB prototype device for merging commonly used peripheral devices," 2015 International Conference on Industrial Instrumentation and Control (ICIC), Pune, 2015, pp. 17-22. DOI: https://doi.org/10.1109/IIC.2015.7150584
Zainalabedin Navabi, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification, 2nd Edition, McGraw-Hill, 2005.
Xilinx ISE Web Pack, Ver 12.3. [Online]. Available: www.xi1inx.com.
Xilinx Spartan -3 Family Complete Duta Sheet, Xilinx, San Jose, CA, USA, 2007.
G. Sung, L. Tung, H. Wang and J. Lin, "USB Transceiver with a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication," in IEEE Access, vol. 8, 2020, pp. 69788-69799. DOI: https://doi.org/10.1109/ACCESS.2020.2986510
G. Sung, H. Wang and J. Lin, "Serial interface engine asic with usb physical transceiver based on fpga development board," 2017 IEEE International Conference on Systems, Man, and Cybernetics (SMC), Banff, AB, 2017, pp. 410-413. DOI: https://doi.org/10.1109/SMC.2017.8122639
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05, Intel Corporation, Chennai, India, Mar.29, 2001.
Muthiah, D., and A. Arockia Bazil Raj. "Implementation of high-speed LFSR design with parallel architectures," 2012 IEEE International Conference on Computing, Communication and Applications, 2012, pp. 1-6. DOI: https://doi.org/10.1109/ICCCA.2012.6179137
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