Implementation and evaluation of network-on-chip by using synopsys tool
Corressponding author's email:
khoapv@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.65.2021.133Keywords:
Network-on-Chip, packet switching, mesh topology, CMOS 90nm technology, power consumptionAbstract
For manycore systems, Network-on-chip (NoC) is a well-known efficient method for replacing traditional bus architectures. In this paper, operation of a system-on-chip applying the network-on-chip concept has been successfully demonstrated. Packet switching-based router architecture, network resource interfaces and process elements are designed and implemented using FPGA hardware platform. In addition, a Matlab-based graphical user interface are also provided in order to monitor the network traffic from outside. The proposed hardware was synthesized and analysed using Design Compiler tool and Synopsys 90nm CMOS technology to obtain timing, and power consumption results.
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