Low power cam memory design using power gating technique
Corressponding author's email:
huanvm@hcmute.edu.vnKeywords:
Content addressable memory (CAM), Match line, Bit Parity, Power gating, Low powerAbstract
In this paper, the author has designed and simulated low-power CAM memory. Content address memory (CAM) will compare stored data with search data and return the appropriate address. CAM is used in applications of packet forwarding and packet sorting in network routers. The article designates a conventional CAM memory and a proposed CAM memory. The proposed CAM memory is designed to reduce overall energy consumption. The proposed CAM memory is designed using power gating technique to cut off the consumption current during CAM data comparison. In addition, this study applies proposed CAM memory to design parity bit checker to reduce delay and consumption power. The author uses Cadence software to perform conventionally and proposed CAM simulations to find the results in comparing those two memories. Based on the results of the simulation, the match-line current is reduced by 59.3%, the delay time is reduced by half and the proposed CAM leakage current is reduced by 96.6% compared to conventional CAM in 45nm CMOS technology.
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References
Kostas Pagiamtzis, Ali Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey” IEEE Journals & Magazines, Vol.41, Issue 3, pp.712-727, 2006.
A.T.Do, S.S.Chen, Z.H.Kong, and K.S.Yeo, “A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing” IEEE Journals & Magazines, Vol.21, Issue 1, pp.151-156, 2013.
Shixiong Jiang, Pengzhan Yan, Ramalingam Sridhar, “A High Speed and Low Power Content-addressable Memory(CAM) Using Pipelined Scheme” IEEE Conferences, pp. 345 – 349, 2015.
Sanghyeon Baeg, “Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line” IEEE Journals & Magazines, Vol.55, Issue 6, pp.1485-1494, 2008.
A. Ragasaratha Preethee; V. Bharathi, “Low power CAM design using modified SCN based classifier”, 2016 10th International Conference on Intelligent Systems and Control (ISCO), 2016.
Duc-Hung Le; Nobuyuki Sugii; Shiro Kamohara; Hong-Thu Nguyen; Koichiro Ishibashi; Cong-Kha Pham, “A 400mV 0.59mW low-power CAM-based pattern matching system on 65nm SOTB process”, TENCON 2015 - 2015 IEEE Region 10 Conference, 2015.
Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, and Kyeong-Sik Min, “Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes,” IEICE Electronics Express, vol. 8, no. 4, pp. 232-238, Feb. 2011
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