Research on the interconnection technologies between dies in the three-dimensional integrated circuits (3-d ics)
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Research, Three-dimensional interconnect technologies, the three-dimensional integrated circuits (3-d ics)Abstract
Three-dimensional interconnect technologies have been proposed in order to mitigate design challenges posed by VLSI such as SoC. By providing multiple layers in integrated circuits together with high-density local interconnects between these layers, 3-D technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect- dominated. In this paper, we will discuss the overall 3-D integration process flow, analysis of 3-D integrated circuits, wire-length performance of 3-D integrated circuits, timing characteristics and energy characteristics of 3-D ICs
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References
Krishna C. Saraswat, K. Banerjee, A. R. Joshi, P. Kalavade, P. Kapur and S. J. Souri, 3-D ICs: Motivation, Performance Analysis, and Technology, Department of Electrical Engineering, Stanford University, Stanford,CA, 94305, USA.
Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, Mahmut Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, Dept. of CSE, The Pennsylvania State University, University Park, PA 16802, USA
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A. Deutsch et al, “On-chip wiring design challenges for Gigahertz operation,” Proceedings of the IEEE, vol. 89, no. 4, April 2001.
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