Pulse-width modulation strategy for common mode voltage elimination in three-level neutral point clamped inverters with reduced common mode voltage spikes

Abstract

This paper presents a pulse-width modulation strategy for common mode voltage elimination in the three-level neutral point clamped (NPC) inverter with reduced common mode voltage spikes. The strategy utilizes the three zero common mode voltage vectors in the space vector diagram and is implemented by using a carrier-based pulse-width modulation (PWM) technique. Based on the use of three zero common mode voltage vectors, the two PWM patterns can be derived, describing the base voltages and average active switching voltages of the three phases in one sampling period. The common mode voltage spikes are partly due to the deadtime which is mandatory in the real-world switching conditions to avoid shoot-through in the inverters. Hence, the impact of deadtime is analyzed in detail. By taking the deadtime effect into account, the proposed method is capable of reducing spikes in common mode voltage waveform. Simulation and experimental results verify the effectiveness of the strategy.