Architecture optimization of pixel-matrix generator for high speed edge-detector based on FPGA platform
Corressponding author's email:
tapchikhgkdt@hcmute.edu.vnKeywords:
high speed image processing, edge detector, FPGAAbstract
This paper presents a method of optimization for pixel-matrix generator of high speed image-processing system on FPGA platform. This method is based on the layout of the function blocks in FPGA chip to optimize the system for real time processing. The optimized generator has been applied to design the high-speed edge detector using Canny algorithm and the low cost FPGA chip.
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J. CANNY, “A computational approach to edge detection,” IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, vol. VOL. PAMI-8, pp. 679–698, 1986.
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