Design and Evaluation Secure Hash Algorithm SHA-256 On ZynQ-702 Hardware Platform
Corressponding author's email:
phuctq@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.2024.1421Keywords:
Secure hash algorithm, Blockchain, IoT, Co-Processor, FPGAAbstract
Hash function plays an important role in security, widely used in privacy authentication. Secure Hash Algorithm (SHA) is a cryptographic algorithm with internal complex structure using many logical and mathematical transformations to generate 256-bits Message digest. It is almost impossible to implement a hash algorithm by software because it takes CPU a long time to fetch instructions, which can cause low speed and consume computer resources. On the other hand, hash algorithms work more effectively when implemented in hardware because hardware uses bit-level and instruction-level parallel processing. The use of Application-Specific Integrated Circuits (ASICs) can help to accelerate SHA, better performance and lower power consumption. However, FPGA-based systems are much more flexible and reprogrammable, design flow is also cheaper while FPGA is able to optimize speed and power consumption. In this paper, we propose a design that implements the secure hash algorithm SHA-256 and evaluate performance of the hashing system. The results are verified based-on simulation using Xilinx Vivado 2019.1 software.
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